Integrated circuits fabricated in SOI technology rely on electrically isolating similar-type FETs located adjacent to one another. Multi-gate semiconductor devices, e.g., similar-type stacked transistors disposed next to one another, are a common configuration in electrical circuits. As the size of semiconductor integrated circuits continue to decrease, current methods for isolating multi-gate semiconductor devices may cause FET-to-FET body leakage and increased short-channel effects.
Recent trends have moved toward reducing the channel length while attempting to maintain the thickness of the SOI package. Conventional semiconductor device fabrication processes have attempted to address short-channel effect issues by epitaxially growing source/drain regions instead of forming source/drain regions by ion implantation processes. Epitaxy allows formation of deep source drain regions with minimal to no lateral dopant diffusion. The process of epitaxially growing the source/drain regions requires a semiconductor seed layer, such as a silicon seed layer, to be used as a template for the crystalline epitaxial growth. The seed layer has opposite doping with respect to the source/drain. Therefore, the seed layer requires an implant to fully butt the junctions. At narrow pitch and short lengths, however, combining butting implants with the conventional source/drain epitaxially growth process causes back channel leakage effect. Furthermore, at higher energy and high implant doses, the butting implant can damage the seed layer and negatively impact the epitaxial growth.